The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometric size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, a three-dimensional transistor, such as a fin-like field-effect transistor (FinFET), has been introduced to replace a planar transistor. A typical FinFET is fabricated with a thin “fin” (or fin structure) extending up from a substrate. The channel of the FET is formed in this vertical fin, and a gate is formed over (e.g., wrapping around) the channel region of the fin. While existing FinFET fabrication techniques have been generally adequate, they have not been entirely satisfactory in all aspects. Therefore, in order to continue to meet ever-increasing design requirements for FinFET devices at increased functional density and decreased geometric sizes, further advances are needed.